This invention relates to a semiconductor memory, and more particularly to a dynamic storage device which makes use of a capacitor as means for accumulating information.
A memory employing metal-insulator-semiconductor field effect transistors (MISFET's) represented by the so-called MOS (metal-oxide-semiconductor) FET's can easily exploit the dynamic storage action of a capacitor or a stray capacitance, and is therefore used in large numbers from the viewpoints of raising the density of integration, lowering the price, etc. Among the MOS memories, one which as recently been highlighted most is the so-called 1 Trs/cell memory (termed "1-element memory" hereafter) employing one MOSFET and capacitor per bit as, for example, published in `ISSCC Digest of Technical papers,` pp. 140-141, February 1976 by K. Itoh et al. Stored information in the 1-element memory is read out to a data line by bringing the MOSFET of the memory into the "on" state. In accordance with this read-out, the potential of the data line changes in such a manner that charges having been accumulated in the capacitor of the 1-element memory are allotted to the capacitors associated with the data line. Accordingly, the potential of the data line corresponds to the information stored in the 1-element memory. By impressing the potential of the data line on a "read" circuit, the stored information from the 1-element memory is read out. The 1-element memory is disadvantageous in that the "read" level of the stored information is low since the level of the data line is determined by the allotment of the charges. However, the capacitance of the capacitor can be made small by endowing the "read" circuit with a high sensitivity. The 1-element memory is advantageous in that the occupying area per bit in a semiconductor substrate can be made small as a semiconductor integrated circuit since the number of the constituent elements per bit is small.
In memories, such as the 1-element memory, of the type wherein charges accumulated in a capacitor and an information are caused to correspond, the charges accumulated in the capacitor leak through various paths. Therefore, the "read" level which appears on the data line in reading out the stored information varies depending on the period of time of the information holding operation of the memory cell. In the memories of the type as described above, the "read" level which lowers or changes due to the leakage of the charges from the capacitor must not exceed the allowable input level of the "read" circuit, so that only a limited information holding time is exhibited. The memories of this type accordingly hold information only temporarily and are called "dynamic memories."
In the form of a semiconductor integrated circuit, a plurality of memory cells each being built up of the 1-element memory as described above are regularly arrayed in a plurality of columns on a semiconductor substrate and constitute a memory cell array or memory cell mat.
When studying the improvement in the "read" level of the 1-element memory, the inventors discovered that the information holding time of memory cells arranged at an end portion of the memory cell array is shorter by a ratio of 1/2-1/10 as compared with that of memory cells at an inner portion. When the information holding time is short, the cycle for rewriting or refreshing the stored information must be raised, and a serious limitation upon use is imposed on the whole memory system.